Design Verification Engineer
JOB DESCRIPTION
To be responsible for managing technology in projects and providing technical guidance or solutions for work completion
To be responsible for providing technical guidance or solutions
To develop and guide the team members in enhancing their technical capabilities and increasing productivity
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.
To ensure process compliance in the assigned module, and participate in technical discussions or review
JOB REQUIREMENT
5 - 10 years of experience
Hands on experience with Verilog, System Verilog, UVM, debugging waveforms
Knowledge of design flow from specification to implementation and verification
Solid knowledge of Verilog RTL design
Experience on Code Coverage, Functional Coverage, Assertions, …
Prior team or technical leadership, or mentorship, are great value-added assets
WHAT'S ON OFFER
18 paid leaves per year (including 12 annual leaves + 6 personal leaves).
Insurance plan based on full salary + 13th salary + Performance Bonus.
100% full salary in probation period.
Medical Benefit (Personal) and Family based on levels.
Working in a fast paced, flexible, and multinational working environment. Chance to travel onsite (in 49 countries).
Internal Training (Technical & Functional). Scope of English Training.
Working from Mondays to Fridays.
CONTACT
PEGASI – IT Recruitment Consultancy | Email: recruit@pegasi.com.vn | Tel: +84 28 3622 8666
We are PEGASI – IT Recruitment Consultancy in Vietnam. If you are looking for new opportunity for your career path, kindly visit our website www.pegasi.com.vn for your reference. Thank you!
Job Summary
Company Type:
Information Technology & Services
Technical Skills:
Verilog, Hardware, RTL
Location:
Ho Chi Minh, Ha Noi - Viet Nam
Salary:
Negotiation
Job ID:
J01515
Status:
Active