Develop and maintain verification environment for module and SOC level using UVM methodology.

Create and debug test cases and Verification IP.

Write and review verification plan and Verification IP documentation.

Use SystemVerilog assertions to write constraints, checkers, and cover points.

Write and review functional coverage, and perform code coverage analysis.

Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure the smooth running of the business.

As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.

Ability to communicate with stakeholders and cross-site partners

Degree/Master in Electrical/Electronic Engineering.

2 years minimum experience in digital IC Verification (IP and SOC level), Senior and Staff levels will be considered for engineers with more years of experience.

Good English skills in reading, writing, and speaking.

Working experiences from design to silicon are essential.

Experience in SystemVerilog and UVM verification methodology.

Experience in using EDA tools from Synopsys / Cadence.

Knowledge and working experience in one or more of the following is a plus:

Healthcare of Bao Viet

2 – 3 business trips to work at headquarter per year

Follow standard VN labor law

Working conditions are normal for an office environment

Work requires willingness to work a flexible schedule

PEGASI – IT Recruitment Consultancy | Email: recruit@pegasi.com.vn | Tel: +84 28 3622 8666