RTL Engineer

ABOUT CLIENT

Our client is a leading global technology company that provides a wide range of IT services and solutions.

JOB DESCRIPTION

JOB REQUIREMENT

Requires minimum 3 years of experience in the following:

Proficiency in RTL Coding in Verilog

Strong comprehension of digital logic design principles, encompassing combinational and sequential logic, finite state machines, etc.

Capable of translating system-level requirements into detailed micro-architecture

Familiarity with AMBA protocol - AHB, APB, AXI

Familiarity with Field BIST implementation and coding

Aptitude for identifying, analyzing, and resolving design issues

Strong communication skills to collaborate effectively with other engineers

Experience with scripting languages such as Perl, Python, or Tcl is a plus

Experience with simulation, testbench development, and potentially formal verification techniques

WHAT'S ON OFFER

This position offers hybrid working arrangements, with three days working in the office and flexible hours.

Salary is negotiable based on candidate expectations.

Employees are entitled to 18 paid leaves annually, which includes 12 annual leaves and 6 personal leaves.

The insurance plan includes coverage based on full salary, a 13th-month salary, and performance bonuses.

A monthly meal allowance of 730,000 VND is provided.

Employees receive 100% full salary and benefits from the start of employment.

Medical benefits are extended to the employee and their family.

The work environment is fast-paced, flexible, and multicultural with opportunities for travel to 49 countries.

The company provides complimentary snacks, refreshments, and parking facilities.

Internal training programs covering technical, functional, and English language skills are offered.

The regular working hours are from 08:30 AM to 06:00 PM on Mondays to Fridays, inclusive of meal breaks.

CONTACT

PEGASI – IT Recruitment Consultancy | Email: recruit@pegasi.com.vn | Tel: +84 28 3622 8666

We are PEGASI – IT Recruitment Consultancy in Vietnam. If you are looking for new opportunity for your career path, kindly visit our website www.pegasi.com.vn for your reference. Thank you!

Job Summary

Company Type:

Outsource

Technical Skills:

Chip RTL Design, RTL

Location:

Ho Chi Minh, Ha Noi - Viet Nam

Working Policy:

Hybrid

Salary:

Negotiation

Job ID:

J01902

Status:

Related Job:

Senior Deep Learning Algorithms Engineer

Ho Chi Minh, Ha Noi - Viet Nam

Product

Machine Learning
Algorithm

Analyze and optimize deep learning training and inference workloads on advanced hardware and software platforms. Work with researchers and engineers to enhance workload performance. Develop high-quality software for deep learning platforms. Create automated tools for workload analysis and optimization.

Negotiation

View details

Software Engineer

Ho Chi Minh - Viet Nam

Product

Create and develop the API Platform with a focus on reliability, performance, and providing a top-tier developer experience Deploy and enhance AI/ML models in scalable, production environments in collaboration with research and applied ML teams Manage and advance a contemporary, cloud-native infrastructure stack utilizing Kubernetes, Docker, and infrastructure-as-code (IaC) tools Ensure platform dependability by designing and implementing telemetry, monitoring, alerting, autoscaling, failover, and disaster recovery mechanisms Contribute to developer and operations workflows, encompassing CI/CD pipelines, release management, and on-call rotations Work collaboratively across teams to implement secure APIs with fine-grained access control, usage metering, and billing integration Continuously enhance platform performance, cost-efficiency, and observability to accommodate scaling and serve users globally.

Negotiation

View details

Physical Design Engineer (STA Focus)

Ho Chi Minh, Ha Noi - Viet Nam

Outsource

Chip Physical Design

Conducting Static Timing Analysis (STA), validation, and debugging under various PVT conditions using Tempus. Implementing DMMMC flow for STA and logical/physical aware ECO flows with a focus on timing and leakage optimization. Overseeing STA setup, convergence, reviews, and final approval for multi-mode (func/scan/atspeed) and multi-voltage domain designs. Evaluating unconstrained endpoints and examining timing reports. Working closely with design, synthesis, and PnR teams to ensure efficient timing closure.

Negotiation

View details