Senior Technical Game Designer
JOB DESCRIPTION
JOB REQUIREMENT
WHAT'S ON OFFER
CONTACT
Job Summary
Company Type:
Product
Technical Skills:
Game Design
Location:
Ho Chi Minh - Viet Nam
Working Policy:
Salary:
Negotiation
Job ID:
J01424
Status:
Close
Related Job:
Physical Design Engineer (HCM)
Ho Chi Minh, Ha Noi, Da Nang, Others, Hai Phong - Viet Nam
Outsource
- Chip Physical Design
We are seeking a Physical Design Engineer responsible for executing and owning the RTL-to-GDSII implementation flow for ASIC/SoC designs. The role includes floorplanning, place & route, timing closure, power integrity, and physical verification, ensuring high-quality, tape-out-ready silicon. Execute complete RTL / Gate-level Netlist to GDSII flow for blocks or full chip. Ownership of physical implementation of design partitions/blocks. Responsible for delivering timing clean blocks that meet sign-off targets including DRC, LVS & IR closure for tape-out readiness. Floor planning & Power Planning Timing Closure & STA CTS & Signal Integrity Physical Verification & Sign-off
Negotiation
View detailsDesign Verification Engineer
Ho Chi Minh, Ha Noi - Viet Nam
Outsource
- Chip Verification
To be responsible for managing technology in projects and providing technical guidance or solutions for work completion To be responsible for providing technical guidance or solutions To develop and guide the team members in enhancing their technical capabilities and increasing productivity To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations To ensure process compliance in the assigned module and participate in technical discussions or review.
Negotiation
View detailsSenior RTL Engineer (HCM)
Ho Chi Minh - Viet Nam
Outsource
- Chip RTL Design
- RTL
We are looking for an RTL IP-Level Design Engineer responsible for designing, integrating, and ensuring the quality of RTL IPs through comprehensive static and functional quality checks. The role involves ownership of RTL from development through quality signoff prior to backend handoff. RTL Design & IP Development Develop synthesizable RTL (Verilog / SystemVerilog) for IP blocks and subsystems based on micro-architecture specifications. Implement clean, scalable, and reusable IP RTL following coding guidelines and industry best practices. Design and maintain wrappers, parameterized RTL, and configuration logic. IP Integration & SoC Readiness Integrate IPs into subsystem / SoC-level hierarchies. Ensure correct clock, reset, power, and interface connectivity. Support AMBA-based interfaces (AXI/APB/AHB) and peripheral protocols (SPI, I2C, UART). RTL Quality Checks & Signoff - Lint /CDC / RDC analysis