Senior DevOps-CloudOps Engineer (AWS)

JOB DESCRIPTION

The Senior DevOps/CloudOps Engineer (SCE) plays the vital role of designing, implementing, securing, and maintaining all of our Client’s cloud infrastructure in Amazon AWS to deliver high performance, reliability, scalability, availability. The SCE is also entrusted to build systems and logics required for our CI/CD/CD pipelines to be used for all of our development.

JOB REQUIREMENT

3+ years of proven experience architecting and building infrastructure/cloud solutions in Amazon AWS (or Google Cloud, Azure, Alibaba Cloud, etc...) using (or equivalent to) ELB, EC2, S3, CloudFront, RDS, Lambda, VPC, ElasticSearch, API Gateway.
2+ years of advanced Linux administration skills
2+ years of managing a container or orchestration platform (Docker or Kubernetes)
3+ years of experience building sophisticated and highly automated infrastructures
2+ years of experience with source control software such as Git and SVN
3+ years of experience of PHP and Python/Go
 
HUGE PLUS IF YOU ARE/HAVE
Excellent understanding of DevOps/CloudOps best practices, approaches and methodologies
Impeccable leadership skills and able to drive DevOps/CloudOps solutions
Excellent knowledge of security & its best practices
Have experience optimizing, customizing, and developing new capabilities for mail systems (Dovecot/Postfix)
Can learn and adapt new technologies quickly

WHAT'S ON OFFER

Friendly, flexible, and fun working environment
Very attractive salary based on skills and experience
Free office lunch
Coffee, tea, snack bar everyday
Full income tax, insurance paid by company (Net Salary)
13th month of salary
Great opportunity for career development
Company trip, team building, monthly party, etc.

CONTACT

PEGASI – IT Recruitment Consultancy | Email: recruit@pegasi.com.vn | Tel: +84 28 3622 8666
We are PEGASI – IT Recruitment Consultancy in Vietnam. If you are looking for new opportunity for your career path, kindly visit our website www.pegasi.com.vn for your reference. Thank you!

Job Summary

Company Type:

Collaborative software

Technical Skills:

Devops, AWS

Location:

Ho Chi Minh - Viet Nam

Working Policy:

Salary:

Negotiation

Job ID:

J00897

Status:

Close

Related Job:

Senior Staff Engineer

Ho Chi Minh - Viet Nam

Product

  • NestJS
  • Angular
  • Typescript

Revamp and streamline key components throughout the Angular 20 + NestJS codebase. Recognize and integrate architectural enhancements such as modularization, domain distinction, and shared service boundaries. Work closely with the CTO to refine product architecture without disrupting release schedule. Guarantee system efficiency, data integrity, and sustainability through improved design. Analyze crucial code pathways and mentor others in cutting-edge Angular and TypeScript methodologies. Introduce practices that elevate testability, deployment security, and developer productivity. Engage in product design conversations to synchronize engineering endeavors with actual user requirements.

Negotiation

View details

Senior Design Verification Engineer

Ho Chi Minh - Viet Nam

Semiconductor

  • Chip Verification

IP/SOC Design Verification: Perform verification of IP and SoC-level designs to ensure functional correctness and performance. Specification Review: Analyze IP/SOC specifications and architectural documentation to extract key features and define verification requirements. Verification Planning: Develop comprehensive verification plans based on design features and project goals. Testbench Development: Build and maintain reusable, scalable testbenches for simulation and validation. Simulation & Debugging: Execute RTL and gate-level simulations, perform failure analysis, and drive coverage analysis and closure. Methodology & Flow: Contribute to the implementation and continuous improvement of design verification methodologies, tools, and workflows.

Negotiation

View details

Senior RTL Design Engineer

Ho Chi Minh - Viet Nam

Semiconductor

  • Chip RTL Design
  • RTL

Designing IP/SOC blocks and integrating them into the full chip Creating architecture and design for clock, power, and reset systems Designing high-speed interface subsystems, such as PCle, UCle, and Ethernet Developing legacy interface IP subsystems, including UART, SPI, I2C, CPU, DMA, APB, and AXI Conducting sanity checks using simulation, LINT, CDC, RDC, and DFT Providing support for physical implementation, including SDC, synthesis, GCA, STA, and formality

Negotiation

View details