Senior DFT Engineer

ABOUT CLIENT

Our client is a pioneering technology company focused on developing innovative solutions in electric mobility and sustainable transportation. With a commitment to engineering excellence and cutting-edge design, Our client aims to revolutionize the industry by creating accessible, eco-friendly vehicles that enhance the driving experience while promoting environmental sustainability for future generations.

JOB DESCRIPTION

We are looking for a highly motivated Senior DFT Engineer to join our advanced ASIC design team. In this position, you will take the lead in defining and implementing comprehensive Design-for-Test (DFT) strategies for complex SoCs and IPs. Collaboration with Front-end, Backend, and Product Engineering teams will be essential to ensure high test coverage, optimal yield, and cost-effective manufacturing solutions.
**Key Responsibilities**
**DFT Strategy & Architecture:** Define DFT specifications and finalize comprehensive strategies (including MBIST, SCAN, BSCAN, IP-Test, In-system test, and Low-Power DFT) to meet rigorous testing targets and quality goals.
**Implementation & Verification:** Lead the implementation and verification of DFT circuits, ensuring robustness across various design scenarios.
**Timing Closure:** Define DFT-specific SDC (Synopsys Design Constraints) and work closely with Backend Engineers to validate timing constraints and achieve timing closure in test modes.
**Pattern Generation & Silicon Debug:** Generate tester patterns using industry-standard tools; perform silicon bring-up, debug analysis, and failure diagnosis to resolve yield issues.
**Optimization:** Analyze test coverage metrics and drive initiatives to improve coverage while reducing test costs, pin counts, and test time.
**Project Leadership:** Act as a Project Leader or Block Coordinator to manage project schedules, mitigate risks, and ensure on-time tape-out (T/O).

JOB REQUIREMENT

Education: Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related fields.
Experience: A minimum of 2 years of hands-on experience in DFT implementation for ASIC/SoC designs.
Note: Individuals with 8+ years of experience may be considered for Senior Manager or Technical Lead roles.
Note: Individuals with less than 2 years of experience may be considered for Junior Engineer roles.
Tool Proficiency: Expert knowledge of industry-standard EDA tools, particularly those involved in DFT, Synthesis, Simulation, and Formal Verification.
Scripting & Automation: Strong expertise in scripting languages such as Tcl, Perl, or Csh. Familiarity with AI prompting techniques to enhance engineering productivity is an advantage.
Soft Skills: Excellent communication skills (both written and verbal) and a demonstrated ability to work effectively in a team.
Language: Proficiency in English is required for effective communication and collaboration in a global environment.

WHAT'S ON OFFER

Work on advanced FinFET technologies with leading global clients.
Join a truly international team with opportunities to collaborate across Asia and the US.
Enjoy a competitive compensation package and opportunities for career growth in a prominent ASIC design service sector.
Experience a collaborative culture that emphasizes innovation and technical excellence.
Equal Opportunity Statement
We are committed to being an equal-opportunity employer. Our focus is on creating an inclusive, diverse, and respectful workplace where all individuals are treated fairly, regardless of background. All hiring decisions are based solely on qualifications, competencies, and business needs.

CONTACT

PEGASI – IT Recruitment Consultancy | Email: recruit@pegasi.com.vn | Tel: +84 28 3622 8666
We are PEGASI – IT Recruitment Consultancy in Vietnam. If you are looking for new opportunity for your career path, kindly visit our website www.pegasi.com.vn for your reference. Thank you!

Job Summary

Company Type:

Product

Technical Skills:

Location:

Ho Chi Minh - Viet Nam

Working Policy:

Onsite

Job ID:

J02335

Status:

Active

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