Senior RTL Design Engineer

IP / SOC block design, and full chip integration

Coherent backbone & local bus architecting and design

Clock/power/reset architecting and design

Legacy interface IP subsystem design: UART, SPI, I2C, etc.

Sanity check (Simulation, Lint, CDC, DFT)

Physical implementation support (SDC script)

5+ years of experience in related work (RTL design and SOC architecting), experiences in sub-system integration & Synopsys Design Constraints (SDC) is preferred

Understanding SOC design flow and methodology

Experience on high-performance low power SOC design and implementation

Good understanding of SOC specifications, architecture, and how to implement high-performance energy-efficient SOC

Functional safety design experience for automotive SOCs

Good understanding of how to co-design software and hardware

Domain knowledge for CPU, coherent/noncoherent cache system, SOC bus, DRAM controller, accelerators (NPU, GPU, DSP), multimedia, and display IP (ISP, video codec, HDMI/DP)

Experience in physical design as well as logical design for big SOC

Competitive and attractive salary

13th salary and performance bonus

Working time: 08: 30 to 5: 30 from Monday to Friday

Private Insurance

Meal Allowance

Monthly team building allowance

Free snack

Onsite working, flexible time

PEGASI – IT Recruitment Consultancy | Email: recruit@pegasi.com.vn | Tel: +84 28 3622 8666