Senior RTL Design Engineer

Designing IP/SOC blocks and integrating them into the full chip

Creating architecture and design for clock, power, and reset systems

Designing high-speed interface subsystems, such as PCle, UCle, and Ethernet

Developing legacy interface IP subsystems, including UART, SPI, I2C, CPU, DMA, APB, and AXI

Conducting sanity checks using simulation, LINT, CDC, RDC, and DFT

Providing support for physical implementation, including SDC, synthesis, GCA, STA, and formality

Over 3 years of experience in related work, including RTL design and SOC architecting, with a focus on sub-system integration, IP development, and familiarity with Synopsys Design Constraints (SDC).

Proficient in SOC design flow and methodology, specifically in the area of high-performance, low-power SOC design and implementation.

Strong grasp of SOC specifications, architecture, and the ability to implement high-performance energy-efficient SOCs.

Experience in functional safety design for automotive SOCs.

Understanding of software and hardware co-design principles.

Expertise in CPU, coherent/noncoherent cache systems, SOC bus, DRAM controller, accelerators (NPU, GPU, DSP), and multimedia and display IP (ISP, video codec, HDMI/DP).

Familiarity with physical and logical design for large SOCs.

We offer a competitive and appealing salary package

13th salary and performance bonuses are included

The working schedule is Monday to Friday

Private insurance coverage is provided

Meal allowance is available

We provide a monthly team building allowance

Free snacks are offered

Onsite work with flexible hours

PEGASI – IT Recruitment Consultancy | Email: recruit@pegasi.com.vn | Tel: +84 28 3622 8666